An Electronic Device Package

ABSTRACT

An electronic device package includes a semiconductor chip having a contact pad on a main face of the semiconductor chip, a contact element disposed on the contact pad, a dielectric layer disposed on the semiconductor chip and the contact element, and an encapsulant disposed onto the dielectric layer.

TECHNICAL FIELD

This disclosure relates in general to a method for fabricating anelectronic device package, to an electronic device package, and to anelectronic voltage converter module. The disclosure relates inparticular to an electronic device package like, for example, a highpower module comprising a dielectric layer and an encapsulant, bothacting together for improving performance and reliability.

BACKGROUND

In many technical areas it is necessary to employ voltage or currentconverters such as DC/DC converters, AC/DC converters, DC/AC converters,or buck converters. For future energy supply, for example, smartelectricity grids connect decentralized renewable energy sources. Incase of wind energy the turbines generate AC power, but for transmissionDC power with lower energy losses is needed. Therefore, smart gridsconsist essentially of high voltage direct current transmission unitswith corresponding converter stations, where several tens of thousandsof high power modules are required. Also in other technical areas, suchconverters are used in order to generate the currents, voltages and/orfrequencies that are intended to be used by an electronic circuit suchas a motor drive circuit, for example. The converter circuits in generalcomprise one or a plurality of half-bridge circuits, wherein each can beprovided by two semiconductor power switches such as, for example, powerMOSFET components or power insulated gate bipolar transistors (IGBT) andfurther components such as, for example, diodes which are connected inparallel with the transistor components, and passive components such as,for example, inductances and capacitances. Electronic modules containingsuch kinds of electrical circuits can be exposed sometimes to very harshconditions like, for example, high humidity.

SUMMARY

In accordance with one aspect of the disclosure a method for fabricatingan electronic device package comprises providing a carrier, disposing atleast one semiconductor chip onto the carrier, the semiconductor chipcomprising at least one contact pad on a main face thereof remote fromthe carrier, applying a contact element onto the contact pad, applying adielectric layer onto the carrier, the semiconductor chip, and thecontact element, and applying an encapsulant onto the dielectric layer.

In accordance with one aspect of the disclosure an electronic devicepackage comprises at least one semiconductor chip comprising at leastone contact pad on a main face thereof, a contact element disposed onthe contact pad, a dielectric layer disposed on the semiconductor chipand the contact element, and an encapsulant disposed on the dielectriclayer.

In accordance with one aspect of the disclosure an electronic voltageconverter module comprises a plurality of semiconductor transistorchips, each one of the semiconductor transistor chips comprising atleast one contact pad on a main face thereof, a contact element disposedon each one of the contact pads, a dielectric layer disposed on thesemiconductor transistor chips and the contact elements, and anencapsulant disposed on the dielectric layer, wherein the semiconductortransistor chips are electrically interconnected to form one or more ofa motor drive circuit, a half-bridge circuit, an AC/AC convertercircuit, a DC/AC converter circuit, a DC/DC converter circuit, and abuck converter circuit.

The person skilled in the art recognizes additional features andadvantages upon reading the following detailed description and upongiving consideration to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of examples and are incorporated in and constitute a partof this specification. The drawings illustrate examples and togetherwith the description serve to explain principles of examples. Otherexamples and many of the intended advantages of examples will be readilyappreciated as they become better understood by reference to thefollowing detailed description.

The elements of the drawings are not necessarily to scale relative toeach other. Like reference numerals designate corresponding similarparts.

FIG. 1 shows a flow diagram for illustrating a method for fabricating anelectronic device package according to a first aspect.

FIGS. 2A-2E illustrate in schematic form examples of applying adielectric layer onto a carrier, in particular depositing a material ofa dielectric layer onto the carrier, including potting/filling (2A),spin coating (2B), spray/jet coating or electrostatic and/or atomizingcoating (2C), laminating (2D), and dipping (2E).

FIGS. 3A-3D show schematic cross-sectional side view representations forillustrating an exemplary method for fabricating an electronic devicepackage according to the first aspect wherein a copper plate or aleadframe is used as a carrier.

FIGS. 4A-4D show schematic cross-sectional side view representations forillustrating an exemplary method for fabricating an electronic devicepackage according to the first aspect wherein a directed bonded copper(DCB) or an insulated metal substrate (IMS) is used as a carrier.

FIGS. 5A-5C show schematic cross-sectional side view representations forillustrating an exemplary method for fabricating an electronic devicepackage wherein a directed bonded copper (DCB) or an insulated metalsubstrate (IMS) is used as a carrier and wire bonds are used forconnecting an upper contact element with the DCB or IMS.

FIG. 6 shows a schematic cross-sectional side view representation of anelectronic device package fabricated by the method as illustrated inFIGS. 3A-3D wherein the carrier was removed after encapsulation.

FIG. 7 shows a schematic cross-sectional side view representation of anelectronic device package fabricated by the method as illustrated inFIGS. 4A-4D wherein the carrier was removed after encapsulation.

FIG. 8 shows a schematic cross-sectional side view representation of anelectronic device package fabricated by the method as illustrated in.FIGS. 5A-5C wherein the carrier was removed after encapsulation.

DETAILED DESCRIPTION

The aspects and examples are now described with reference to thedrawings, wherein like reference numerals are generally utilized torefer to like elements throughout. In the following description, forpurposes of explanation, numerous specific details are set forth inorder to provide a thorough understanding of one or more aspects of theexamples. It may be evident, however, to one skilled in the art that oneor more aspects of the examples may be practiced with a lesser degree ofthe specific details. In other instances, known structures and elementsare shown in schematic form in order to faciltate describing one or moreaspects of the examples. It is to be understood that other examples maybe utilized and structural or logical changes may be made withoutdeparting from the scope of the present disclosure. It should be notedfurther that the drawings are not to scale or not necessarily to scale.

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific aspects in which the disclosure may bepracticed. In this regard, directional terminology, such as “top”,“bottom”, “front”, “back” etc., may be used with reference to theorientation of the figures being described. Since components ofdescribed devices may be positioned in a number of differentorientations, the directional terminology may be used for purposes ofillustration and is in no way limiting. It is understood that otheraspects may be utilized and structural or logical changes may be madewithout departing from the scope of the present disclosure. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present disclosure is defined bythe appended claims.

In addition, while a particular feature or aspect of an example may bedisclosed with respect to only one of several implementations, suchfeature or aspect may be combined with one or more other features oraspects of the other implementations as may be desired and advantageousfor any given or particular application. Furthermore, to the extent thatthe terms “include”, “have”, “with” or other variants thereof are usedin either the detailed description or the claims, such terms areintended to be inclusive in a manner similar to the term “comprise”. Theterms “coupled” and. “connected”, along with derivatives may be used. Itshould be understood that these terms may be used to indicate that twoelements co-operate or interact with each other regardless whether theyare in direct physical or electrical contact, or they are not in directcontact with each other. Also, the term “exemplary” is merely meant asan example, rather than the best or optimal. The following detaileddescription, therefore, is not to be taken in a limiting sense, and thescope of the present disclosure is defined by the appended claims.

The examples of a method for fabricating an electronic device package,of an electronic device package and of an electronic voltage convertermodule may use various types of semiconductor devices. The examples mayuse transistor devices embodied in semiconductor dies or semiconductorchips wherein the semiconductor dies or semiconductor chips may beprovided in a form of a block of semiconducting material as fabricatedfrom a semiconductor wafer and diced out from the semiconductor wafer,or in another form in which further process steps have been carried outlike, for example, applying an encapsulation layer to the semiconductordie or semiconductor chip. The examples may also use horizontal orvertical transistor devices wherein those structures may be provided ina form in which all contact elements of the transistor device areprovided on one of the main faces of the semiconductor die (horizontaltransistor structures) or in a form in which at least one electricalcontact element is arranged on a first main face of the semiconductordie and at least one other electrical contact element is arranged on asecond main face opposite to the main face of the semiconductor die(vertical transistor structures) like, for example, MOS transistorstructures or IGBT (Insulated Gate Bipolar Transistor) structures.Insofar as the transistor chips are configured as power transistor chipsand if in addition also driver chips are integrated into the package,the examples of an electronic device package disclosed further below canbe classified as intelligent power modules (IBM).

In any case the electronic devices, e.g. the semiconductor dies orsemiconductor chips, may comprise contact elements or contact pads onone or more of their outer surfaces wherein the contact elements areelectrically connected with the electrical circuit, e.g. the transistor,of the respective semiconductor die and serve for electricallyconnecting the semiconductor die to the outside. The contact elementsmay have any desired form or shape. They can, for example, have the formof lands, i.e. flat contact layers on an outer surface of thesemiconductor die. The contact elements or contact pads may be made fromany electrically conducting material, e.g. from a metal as aluminum,gold, or copper, for example, or a metal alloy, or an electricallyconducting organic material, or an electrically conducting semiconductormaterial. The contact elements may also be formed as layer stacks of oneor more of the above-mentioned or further materials so as to create, forexample, a stack of NiPdAu.

The examples of an electronic device package may comprise an encapsulantor encapsulating material having the semiconductor transistor chipsembedded therein. The encapsulating material can be any electricallyinsulating material like, for example, any kind of molding material, anykind of resin material, or any kind of epoxy material, a bismaleimide,or a cyanate ester. The encapsulating material can also be a polymermaterial, a polyimide material, a thermoplast material, a ceramicmaterial, and a glass material. The encapsulating material may alsocomprise any of the above-mentioned materials and further include fillermaterials embedded therein like, for example, thermally conductiveincrements. These filler increments can be made of SiO, Al2O3, ZnO, AlN,BN, MgO, Si3N4, or ceramic, or a metallic material like, for example,Cu, Al, Ag, or Mo. Furthermore, the filler increments may have the shapeof fibers and can be made of carbon fibers or nanotubes, for example.

Insofar as methods for fabricating an electronic device package aredescribed as having a specific order of method steps, it should bementioned that any other appropriate order of the method steps may beemployed by the skilled person. It should further be mentioned that anycomments, remarks or features mentioned in connection with a describedmethod are to be understood as also disclosing a device being obtainedor resulting from such comments, remarks or features, even if such adevice is not explicitly described or illustrated in the figures.Furthermore, any comments, remarks or features mentioned in connectionwith a device are to be understood as also disclosing a method step forproviding or fabricating the respective device feature.

FIG. 1 shows a flow diagram for illustrating a method for fabricating anelectronic device package according to a first aspect. The methodcomprises providing a carrier (s1), disposing at least one semiconductorchip onto the carrier, the semiconductor chip comprising at least onecontact pad on a main face (s2), applying a contact element onto thecontact pad (s3), applying a dielectric layer onto the carrier, thesemiconductor chip, and the contact element (s4), and applying anencapsulant onto the dielectric layer (s5).

According to an example of the method according to the first aspect, thematerial of the dielectric layer is chosen such that it may function ina best possible way as a stress buffer between the semiconductor chipand the encapsulation layer, and furthermore that it may in a bestpossible way function as a barrier against humidity which may penetratefrom the environment, and also to function in a best possible way toelectrically isolate the semiconductor chip, i.e. the electrical devicesdisposed in the semiconductor chip.

According to an example of the method according to the first aspect, thedielectric layer is one or more of a polymer layer, a polyimide layer, aparylene layer, a polybenzoxazole (PBO) layer, a resin layer, inparticular an epoxy resin layer, a silicone layer, a spin-on glasslayer, and also hybrid materials, i.e. compound materials of one or moreof the above mentioned materials like, for example, a compound ofmaterials exhibiting similar, different, or overlapping properties, e.g.PBO and a polyimide. In particular, such hybrid materials could be usedwhich combine opposed or contrary properties e.g. organic and inorganicmaterials. The dielectric layer can also be a semiconductor oxide orsemiconductor nitride or semiconductor oxynitride layer like, e.g. aSiO, a SiN or a SiON layer.

According to an example of the method according to the first aspect, thedielectric layer does not include any filler materials or increments,but is essentially a homogenous layer of any one of the above-mentionedmaterials. It is, however, likewise possible that the dielectric layerincludes filler materials or increments, wherein the filler incrementscan be selected such that they fulfill particular functions like, forexample, ion catching, flame inhibiting, softening or plasticizing.

According to an example of the method according to the first aspect, thedielectric layer comprises one or more of the following properties: adielectric constant in a range from 2 to 5, a dielectric strength in arange from 100 to 500 V/μm, a dissipation factor in a range from 0.005to 0.03, and a modulus of elasticity in a range from 0.1 to 5.0 GPa,wherein the dissipation factor is a measure of the dielectric losses inan electrically insulating material when used in an alternating field.

According to an example of the method of the first aspect, applying thedielectric layer comprises depositing the dielectric layer whereindepositing the dielectric layer comprises one or more of spin coating,spray coating or jet coating or electrostatic and/or atomizing coating,wave coating, potting, filling, laminating, in particular vacuumlaminating, dipping, physical vapor deposition (PVD), chemical vapordepositing (CVD), or printing.

According to an example of the method according to the first aspect,applying the dielectric layer further comprises heating or curing thedeposited dielectric layer. According to a further example thereof, aheating temperature is in a range up to 500° C., in particular from 80°C. to 400° C., in particular from 150° C. to 280° C., and the heatingtime is in a range up to 5 h, in particular from 0.5 h to 3.0 h, inparticular 1 h to 2 h. According to a further example thereof, beforethe heating a pre-heating or pre-bake can be carried out at, forexample, a pre-heating temperature in a range from 80° C. to 140° C., inparticular from 100° C. to 120° C., and at a heating time in a range upto 20 min. The pre-heating step may prove to be advantageous fordehumidifying the deposited dielectric layer and to evaporate thesolvent.

According to an example of the method according to the first aspect,applying the dielectric layer comprises applying a stack of two or moredielectric layers of one or more of different materials or of differentproperties. Hence, either the materials of the two or more dielectriclayers are different or the materials of the two or more dielectriclayers are similar or equal but their properties are different. If thematerials are different from each other then, in general, also theirproperties will be different. If the materials are similar or equal,their properties can be different. For example, in the case of polyimidelayers or other kinds of polymeric layers, they can be treated in adifferent way after deposition so that the degree of forming a networkof polymers or atoms, in particular the polymerisation or ofcross-linking of the molecules, in case of a polyimide layer theimidization of the polyimide layers, can be different from each other.According to an example thereof, the method may further comprisedepositing a first dielectric layer and treating the deposited firstdielectric layer with a first set of conditions, and depositing a seconddielectric layer and treating the deposited second dielectric layer witha second set of conditions, wherein the first set of conditions isdifferent from the second set of conditions. As a further examplethereof, the first set of conditions comprises a first heatingtemperature and first heating time, and the second set of conditionscomprises a second heating temperature and a second heating time. If,for example, the first dielectric layer is comprised of a firstpolyimide layer and the first heating temperature is in a range between300° C. and 350° C., the result will be a polyimide layer with a degreeof imidization equal to or near to 100%. If then, for example, thesecond dielectric layer is also comprised of a polyimide layer and thesecond heating temperature is in a range between 200° C. and 250° C.,then the result will be a second polyimide layer having a degree ofimidization significantly less than 100%, i.e. 95% or even less thanthat. It is also possible to choose the same heating temperatures forthe two different layers, but different heating times. Moreover, thedescribed variant of depositing two or more dielectric layers andtreating them with different conditions can also be applied to the othermaterials mentioned above for use as dielectric layer. According to aspecific example, a first lower layer can be a silicone layer and asecond upper layer can be a polyimide layer.

According to an example of the method of the first aspect, applying theencapsulant comprises applying a host material comprising one or more ofa resin, in particular an epoxy resin, an epoxy silicone, or an epoxypolyimide, a bismaleimide, a cyanate ester, or a thermoplast. Accordingto an example thereof, the host material comprises filler incrementsembedded therein, wherein the filler increments can be made of SiO,Al2O3, MgO, AlN, Si3N4, BN, or another ceramic material. The fillerincrements can also be selected such that they fulfill particularfunctions like, for example, ion catching, flame inhibiting, softeningor plasticizing, or stress releasing.

According to an example of the method of the first aspect, applying theencapsulant comprises one of transfer molding, compression molding,vacuum casting, or laminating.

According to an example of the method of the first aspect, theencapsulant is applied with a thickness in a range from 0.1 mm to 10 mm,in particular from 1 mm to 5 mm. It should be noted in this respect thatin most cases the encapsulant is applied to a surface which is notplanar but instead a more or less complex three-dimensional structure sothat the above values may refer to a thickness of the encapsulant aboveany location of this three-dimensional structure.

According to an example of the method of the first aspect, afterapplying the dielectric layer, i.e. after depositing and curing of thedielectric layer, a post-treatment can be carried out in order toincrease the surface purity and hence increase the adhesion propertiesof the dielectric layer with respect to the later to be depositedencapsulation layer. The post-treatment may comprise, for example, aplasma treatment or plasma activation for increasing the adhesionconditions for the encapsulation layer. The post-treatment may insteador in addition comprise the deposition of a special adhesion promotorlayer which can be, for example, a silane layer or a zinc chromium oxidelayer.

According to an example of the method of the first aspect, thedielectric layer can be structured so that it contains openings orthrough-holes of any desired lateral dimensions and numbers. If thedielectric layer is deposited as a whole like, for example, in the formof a laminate layer, the structuring can be carried out beforedepositing the laminate layer or after depositing the laminate layer. Ifthe dielectric layer is deposited in a sequential manner with anyone ofthe methods as described above, the structuring may be carried outduring the depositing of the dielectric layer by, for example, using amask having openings, or it may be carried out after depositing of thedielectric layer on the whole area and as a further example thereof itmay be carried out either before or after the curing. The structuringcan then, for example, be carried out by laser ablation or laser directimaging or by photolithographic or lift-off techniques.

According to an example of the method of the first aspect, thesemiconductor chips each comprise a transistor comprising a gatecontact, an emitter contact, and a collector contact, and thetransistors are each configured to function with an emitter collectorvoltage above 1200 V. However, the present disclosure is not limited tothis voltage range and is also applicable in the voltage class below1200 V or, for example, in the automotive, aerospace, or medical area,or in general in technological areas in which reliability is animportant factor or even the most important factor.

According to an example of the method of the first aspect, the carriercan be an auxiliary or temporary carrier which is removed after applyingthe encapsulant so that the carrier will not be part of the fabricatedelectronic device package.

According to an example of the method of the first aspect, the carrierwill not be removed and will be part of the fabricated electronic devicepackage in which case the carrier functions as a chip carrier. The chipcarrier can be a conductive carrier like, for example, a metal carrier,a copper plate, a molybdenum plate, or a leadframe, or a direct copperbond (DCB), or an insulated metal substrate (IMS). It should bementioned, however, that also in this case an additional auxiliary ortemporary carrier can be used onto which the chip carrier is disposed.This offers the possibility to apply different kinds of chip carriersonto the auxiliary or temporary carrier. Lateran the chips or chipmodules can be encapsulated on 5 sides, i.e. at their 4 side faces andon their upper main face.

FIGS. 2A-2E show in a schematic form different methods of depositing thedielectric layer. In FIGS. 2A-2D, an electronic device module 10 isshown which comprises a carrier 11 and a plurality of semiconductorchips 12 disposed on the carrier 11. Moreover, electrical contactelements (not shown) are disposed onto the semiconductor chips 12. FIG.2A shows a process of potting or filling of a liquid dielectric material13 onto the electronic device module 10. A dispenser 14 is positionedabove the electronic device module 10 and delivers the liquid material13 onto the upper main surface of the electronic device module 10 wherethe liquid material 13 is distributed over the entire upper surface.FIG. 2B shows a process of spin coating where essentially in addition tothe process of FIG. 2A, the electronic device module 10 is rotatedaround a vertical axis as shown by the arrow in order to optimallydistribute the liquid material 13 on the upper surface of the electronicdevice module 10. FIG. 2C shows a process of spray or jet coating of theliquid or partly dried material 13 by using a dispenser 24 which is ableto deliver the liquid material 13 in the form of a spray jet whichextends over a spatial angle in order to cover a certain area of theupper surface of the electronic device module 10. In addition, eitherthe dispenser 24 or the electronic device module 10 can be movedlaterally as indicated by the arrows. FIG. 2D shows a method oflaminating the dielectric layer onto the electronic device module 10. Inthis method, a prefabricated dielectric laminate foil 23 is depositedonto the upper surface of the electronic device module 10 by use of anadhesion agent. FIG. 2E shows a process of dipping the electronic devicemodule 10 into a container which contains a liquid 33 of the dielectricmaterial to be deposited. The dielectric material will adhere to theupper surface of the electronic device module 10 after dipping it intothe bath of the liquid 33.

It should be mentioned that in the representation of FIGS. 2A-2E thereference sign. 12 can also refer to semiconductor modules includingeach a plurality of semiconductor chips and the reference sign 10 canrefer to a chip carrier panel having deposited thereon a plurality ofsuch semiconductor modules 12. At the end of the fabrication process orafter encapsulating the chip carrier panel, an encapsulant panel isobtained and the encapsulant panel can be singulated to obtain aplurality of individual semiconductor modules 12. It is also possiblenot to encapsulate the chip carrier panel but to singulate the chipcarrier panel after the deposition of the dielectric layer andthereafter to encapsulate the individual semiconductor modules. This canbe carried out by placing the individual semiconductor modules onto atemporary carrier, and then applying an encapsulant onto the temporarycarrier and the semiconductor modules, thereby obtaining an encapsulantpanel. Thereafter the encapsulant panel can be singulated into aplurality of encapsulated semiconductor modules.

Furthermore in the representation of FIGS. 2A-2E, the semiconductorchips 12 are not necessarily identical and not necessarily transistorchips. They can also be, for example, sensor chips or logic chips inwhich way an intelligent power module (IPM) as was mentioned above iscreated.

Depending on the material of the dielectric layer, also other methods ofdepositing like, for example, vacuum lamination or printing can beemployed. In case of, for example, parylene as material of dielectriclayer, physical vapor deposition (PVD) or electrostatic and/or atomizingcoating or ion atomizing can be used for depositing the parylene layer.The dielectric material can also be deposited in the form of agranulate, in particular a plastic granulate. In other cases, alsochemical vapor deposition (CVD) may be used as the deposition method.

As already described above, after depositing the dielectric layer it maybe cured at a temperature in a range from 200° C. to 400° C. in, forexample, a batch furnace for a curing time in a range from 1 h to 4 h.The curing atmosphere can be nitrogen (N₂) with low vacuum and/or highervacuum of 500 mbar or even below or above that. This process stepgenerates and guarantees the final material properties throughimidization, polymerzation, x-linking polymer molecules or atoms or anysort of chemical reaction in general. Before this curing process thedielectric layer can be pre-baked and a surface treatment like, forexample, plasma activation, a wet chemical treatment or applying anadhesion promoter, can be performed before applying the encapsulant. Thepre-baking will ensure solvent evaporation and humidity outgassing andthe plasma activation will ensure sufficient adhesion between thedielectric layer and the encapsulant material.

FIGS. 3A-3D show schematic cross-sectional side view representations forillustrating an exemplary method of the first aspect. According to FIG.3A, a chip carrier 30 is provided which may be comprised of a leadframeor a copper plate in this example. The chip carrier 30 can also beapplied onto an auxiliary or temporary carrier which is not shown in theFigure for reasons of clarity. It is possible to dispose different kindsof chip carriers 30 onto the auxiliary carrier, for example in case thata panel comprising a plurality of semiconductor modules is to befabricated on the auxiliary carrier. The auxiliary carrier can beremoved later in the fabrication process. Onto the chip carrier 30 aplurality of semiconductor chips 32 is deposited by use of anintermediate solder or adhesion layer 31. The chips 32 may haveelectrical contact pads 32A on their upper surface and in case of, forexample, vertical transistors also on their lower surface. On the uppersurface of the chips 32 a contact element 33 is applied onto a contactpad 32A. The contact elements 33 may have the form of spacer elementsand may be fabricated by copper either galvanically plated or applied asa whole in the form of copper plates. The contact pad 32A can be, forexample, an emitter contact pad of an insulated gate bipolar transistor(IGBT). A gate contact element of the IGBT can also be provided on theupper surface of the semiconductor chips 32 (not shown) and a gatecontact layer can be applied which provides connections to all gatecontact pads of the semiconductor chips 32.

According to FIG. 3B, a dielectric layer 34 is deposited onto the uppersurfaces of the intermediate product as shown in FIG. 3A, i.e. onto theupper surfaces of the contact elements 33, the semiconductor 32, thesolder layer 31, and the carrier 30, by anyone of the deposition methodsas described before.

According to FIG. 30, after curing of the dielectric layer 34 anencapsulation layer or encapsulant 35 is deposited onto the intermediateproduct as shown in FIG. 3B. The encapsulant 35 can be applied by, forexample, transfer molding, compression molding, vacuum casting, orlaminating.

According to FIG. 3D, the encapsulation layer 35 is partly removed fromabove by, for example, grinding in order to expose the contact elements33 so that they can be connected to further outside electricalconnectors. As will be seen in the next example, grinding is notessential and also other measures can be taken to connect the contactelements 33 to the outside electrical connectors.

FIGS. 4A-4D show schematic cross-sectional side view representations forillustrating an exemplary method for fabricating an electronic devicepackage according to the first aspect. According to FIG. 4A, a carrier40 is provided in the form of, for example, a direct bonded copper (DCB)40. The DCB 40 comprises a substrate 40A comprising an insulating,dielectric or ceramic layer or tile, and a first metallic layer 40B on alower surface of the substrate 40A and a second metallic layer 40C on anupper surface of the substrate 40A. According to an example the carrier40 may comprise one or more of a direct copper bonded (DCB) substrate, adirect aluminum bonded (DAB) substrate, and an active metal brazingsubstrate, wherein the substrate may comprise a ceramic layer, inparticular one or more of AlN, Al₂O₃, or a dielectric layer, inparticular Si₃N₄. The carrier 40 can also refer to an isolated metalsubstrate (IMS) in which similar to a DCB an intermediate insulatinglayer is sandwiched between two metallic layer wherein the intermediateinsulating layer comprises a composite of a host material, in particularwith filler increments like, for example, BN increments or any otherincrements as were mentioned above in connection with the encapsulant.The host material can be anyone of the materials which are mentionedwithin the present disclosure in connection with the encapsulant. DCBand IMS allow electrical isolation to a heatsink and at the same timegood heat transfer to the heatsink, and also electrical isolationbetween the semiconductor chips applied onto the DCB or IMS.

Semiconductor chips 42 are deposited on an upper surface of the carrier40 by use of an intermediate solder or adhesive layer 41 in the same wayas it is described in connection with FIG. 3A. Furthermore, electricalcontact elements 43 are attached to contact pads 42A of thesemiconductor chips 42 which as well corresponds to the disposing ofcontact elements described previously in connection with FIG. 3A.

According to FIG. 4B, a dielectric layer 44 is deposited onto theintermediate product of FIG. 4A in the same way as described above inconnection with FIG. 3B.

According to FIG. 4C, an encapsulation layer or encapsulant 45 isapplied to the intermediate product of FIG. 4B in the same way asdescribed above in connection with FIG. 3C.

According to FIG. 4D, openings 45A are formed in an upper surface of theencapsulant 45, the openings 45A extending from the upper surface downto the electrical contact elements 43 in order to allow connecting thecontact elements 43 to further outside electrical connectors in a laterstep. The forming of the openings 45A can be carried out by laserdrilling, which is capable to remove or ablate not only the material ofthe encapsulant 45 but also the material of the dielectric layer 44.

FIGS. 5A-5C show schematic cross-sectional side view representations forillustrating an exemplary method for fabricating an electronic devicepackage according to the first aspect. According to FIG. 5A, a carrier50 may be provided which may be similar or equal to the carrier 40 ofFIGS. 4A-4D and can thus have the form of a DCB. The carrier 50 can,however, also be similar or equal to the carrier 30 of FIGS. 3A-3D. Asemiconductor chip 52 is deposited onto an upper surface of the carrier50 by use of an intermediate solder or adhesive layer 51 in the same wayas described before in connection with FIG. 3A or FIG. 4A. Instead ofjust one semiconductor chip 52 also a plurality of semiconductor chips52 can be applied onto the upper surface of the carrier 50. Anelectrical contact element 53 is applied to a contact pad. 52A of thesemiconductor chip 52 in the same way as described before in connectionwith FIGS. 3A and 4A. A bond wire 54 is then connected between thecontact element 53 and an upper surface of an area of the carrier 50.Another bond wire 54 can be connected between another contact element 53and an upper surface of another area of the carrier 50. It should bementioned that instead of a bond wire 54 also a clip could be applied asan electrical connection between the contact element 53 and an uppersurface of an area of the carrier 50.

According to FIG. 5B, a dielectric layer 55 is then deposited onto anupper surface of the intermediate product of FIG. 5A in the same way asdescribed before in connection with FIGS. 3B and 4B. As a result, thedielectric layer 55 is also applied to the upper surfaces of the bondwires 54.

According to FIG. 5B, an encapsulation layer 56 is applied to theintermediate product of FIG. 5B in the same way as described before inconnection with FIGS. 3C and 4C.

The present disclosure also relates to an electronic device packageaccording to a second aspect. The electronic device package according tothe second aspect comprises a carrier, at least one semiconductor chipdisposed on the carrier, the semiconductor chip comprising at least onecontact pad on a main face thereof remote from the carrier, a contactelement disposed on the contact pad, a dielectric layer disposed on orabove the carrier, the semiconductor chip, and the contact element, andan encapsulation layer disposed on the dielectric layer.

Further examples of the electronic device package according to thesecond aspect can be formed by incorporating examples or features whichwere described before in connection with the method according to thefirst aspect.

The electronic device package according to the second aspect may, forexample, have a form such as that shown in FIG. 3D, 4D or 5C comprising,respectively, a carrier 30, 40 or 50, at least one semiconductor chip32, 42 or 52, having a contact pad 32A, 42A or 52A, a contact element33, 43 or 53, a dielectric layer 34, 44 or 55, and an encapsulationlayer 35, 45 or 56.

The electronic device package according to the second aspect may alsohave a form such as that shown in FIG. 6, 7 or 8 which refer to the casethat the respective carriers 30, 40 or 50 as shown in FIGS. 3D, 4D, and5C were only used as auxiliary carriers which were removed afterencapsulating. FIG. 6 corresponds to FIG. 3D, FIG. 7 corresponds to FIG.4D and. FIG. 8 corresponds to FIG. 5C, respectively, wherein allreference signs were taken over and have the same meaning as before.

The present disclosure also relates to an electronic voltage convertermodule according to a third aspect. The electronic voltage convertermodule, according to the third aspect, comprises an electronic devicepackage according to the second aspect, wherein the semiconductor chipsare semiconductor transistor chips which are electrically interconnectedto form one or more of a motor drive circuit, a half-bridge circuit, anAC/AC converter circuit, a DC/AC converter circuit, a DC/DC convertercircuit, and a buck converter circuit.

Further examples of the electronic voltage converter module according tothe third aspect can be formed by incorporating examples and featureswhich were described before in connection with the method according tothe first aspect or the electronic device package according to thesecond aspect.

While the invention has been illustrated and described with respect toone or more implementations, alterations and/or modifications may bemade to the illustrated examples without departing from the spirit andscope of the appended claims. In particular regard to the variousfunctions performed by the above described components or structures(assemblies, devices, circuits, systems, etc.), the terms (including areference to a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component or structurewhich performs the specified function of the described component (e.g.,that is functionally equivalent), even though not structurallyequivalent to the disclosed structure which performs the function in theherein illustrated exemplary implementations of the invention.

What is claimed is:
 1. An electronic device package, comprising: asemiconductor chip comprising a contact pad on a main face of thesemiconductor chip; a contact element disposed on the contact pad; adielectric layer disposed on the semiconductor chip and the contactelement; and an encapsulant disposed onto the dielectric layer.
 2. Theelectronic device package of claim 1, further comprising a carrier onwhich the semiconductor chip is disposed.
 3. The electronic devicepackage of claim 2, wherein the carrier is a conductive carrier.
 4. Theelectronic device package of claim 2, wherein the carrier is a directcopper bonded (DCB) substrate.
 5. The electronic device package of claim2, wherein the carrier is an insulated metal substrate (IMS).
 6. Theelectronic device package of claim 2, wherein the carrier is anauxiliary carrier.
 7. The electronic device package of claim 2, whereinthe carrier is a temporary carrier.
 8. The electronic device package ofclaim 1, wherein the dielectric layer comprises one or more of apolyimide layer, a parylene layer, a polybenzoxazole layer, a resinlayer, a silicone layer, a spin-on glass layer, a semiconductor oxidelayer, a semiconductor nitride layer, and a semiconductor oxynitridelayer.
 9. The electronic device package of claim 1, wherein thedielectric layer has a dielectric constant in a range from 2 to
 5. 10.The electronic device package of claim 1, wherein the dielectric layerhas a dielectric strength in a range from 100 V/μm to 500 V/μm.
 11. Theelectronic device package of claim 1, wherein the dielectric layer has adissipation factor in a range from 0.005 to 0.03, and wherein thedissipation factor is a measure of dielectric losses in the dielectriclayer when used in an alternating field.
 12. The electronic devicepackage of claim 1, wherein the dielectric layer has a modulus ofelasticity in a range from 0.1 GPa to 5.0 GPa.
 13. The electronic devicepackage of claim 1, wherein the dielectric layer has a thickness in arange from 2 μm to 100 μm.
 14. The electronic device package of claim 1,wherein the dielectric layer comprises a stack of two or more dielectriclayers of one or more of different materials and of differentproperties.
 15. The electronic device package of claim 1, wherein theencapsulant comprises a host material comprising one or more of a resin,an epoxy silicone, an epoxy polyimide, a bismaleimide, a cyanate ester,and a thermoplast.